1.Responsible for technical management for team and leading team to finish BE tasks.
2.Work as technical expert to support technical team.
3.Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.
4.Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis
5.Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
6.Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.
7.Static Timing analysis (Prime Time) and setup/hold fix.
8.Formal Verification for equivalence checking (Formality).
9.Generation of fill structures according to technology requirements.
1.1-3 years experience for technical team leadership.
2. About 5 years experience in backend design flow (APR) with proven SOC tape-out experience.
3.Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
4.Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
5.Experience and knowledge about FE design (RTL code, flow) and verification is a plus.
6. Good communication in teamwork spirit.
7.Good analytical and debugging skills.
8.Good command of English.